AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

2.8. Step 8: Verifying Hardware with Signal Tap

  1. In the Signal Tap window, click File > Open, and open stp_core_partition_reuse.stp.
  2. Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
  3. In the JTAG Chain Configuration tab, set up the JTAG connection to the board by clicking Setup and then selecting the USB-BlasterII under Hardware.

    The device populates automatically.

    Figure 23. JTAG Scan Configuration
    The Instance Manager window shows Ready to acquire.
    Figure 24. Instance Manager
  4. To set the trigger condition, select count_int[24], right-click the column under Trigger Conditions, and set to Falling Edge.
    Figure 25. Trigger Conditions
  5. Run analysis by clicking Processing > Run Analysis.
    When the analysis finishes, the Waveform tab shows the captured data.
Figure 26. Waveform after Signal Tap Analysis
  • The count_int[27:24] register in u_blinking_led_top|u_counter|count_int[27:24] drives u_blinking_led_top|u_blinking_led|value[3:0].
  • The partition boundary ports created for each bit of value[3:0] are db_value_3, db_value_2, db_value_1, and db_value_0.
  • The value of db_value_0 changes a cycle later after count_int[24] transitions to 0. The count_int[2:0] shows the transitioning of the counter during this process