AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

5. Root Partition Reuse Debug—Consumer

Process Description

The root partition Consumer receives from the Developer the final top-level, placed, and routed root partition, and optionally a .sdc file. Then, the Consumer enables the reserved core partition for debug by instantiating the SLD JTAG Bridge Host, which communicates with the SLD JTAG Bridge Agent instantiated in the root partition. Finally, the Consumer taps pre-synthesis nodes in the Signal Tap GUI to debug the reserved core partition.

Completed Tutorial Files

The Root_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.