AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

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ID 683712
Date 12/21/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Core Partition Reuse Debug—Developer 3. Core Partition Reuse Debug—Consumer 4. Root Partition Reuse Debug—Developer 5. Root Partition Reuse Debug—Consumer 6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives 7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board
1. Introduction x
1.1. Tutorial Software and Hardware 1.2. Tutorial Files 1.3. Signal Tap with Core Partition Reuse 1.4. Signal Tap with Root Partition Reuse
2. Core Partition Reuse Debug—Developer x
2.1. Step 1: Creating a Core Partition 2.2. Step 2: Creating Partition Boundary Ports 2.3. Step 3: Compiling and Checking Debug Nodes 2.4. Step 4: Exporting the Core Partition and Creating the Black Box File 2.5. Step 5: Copying Files to Consumer Project 2.6. Step 6: Creating a Signal Tap File (Optional) 2.7. Step 7: Programming the Device and Verifying the Hardware 2.8. Step 8: Verifying Hardware with Signal Tap
3. Core Partition Reuse Debug—Consumer x
3.1. Step 1: Adding Files and Running Synthesis 3.2. Step 2: Creating a Signal Tap File 3.3. Step 3: Creating a Partition for blinking_led_top 3.4. Step 4: Compiling the Design and Verifying Debug Nodes 3.5. Step 5: Programming the Device and Verifying the Hardware 3.6. Step 6: Verifying Hardware with Signal Tap
4. Root Partition Reuse Debug—Developer x
4.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region 4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition 4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host 4.4. Step 4: Generating HDL Instance of Signal Tap 4.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project 4.6. Step 6: Programming the Device and Verifying the Hardware 4.7. Step 7: Generating a Signal Tap File for the Root Partition 4.8. Step 8: Verifying the Hardware with Signal Tap
5. Root Partition Reuse Debug—Consumer x
5.1. Step 1: Adding Files to Customer Project 5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition 5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling 5.4. Step 4: Programming the Device and Verifying the Hardware 5.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap 5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap
1. Introduction
2. Core Partition Reuse Debug—Developer
3. Core Partition Reuse Debug—Consumer
4. Root Partition Reuse Debug—Developer
5. Root Partition Reuse Debug—Consumer
6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives
7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board

7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board

Document Version Intel® Quartus® Prime Version Changes
2020.12.21 20.3
  • Updated the design example in Tutorial Files.
  • In Step 2: Creating Partition Boundary Ports, updated step 5 with additional information.
  • In Step 6: Creating a Signal Tap File, made minor corrections in step 5.
2019.12.11 19.3
  • In Introduction, added Core Partition Reuse Example.
  • Updated Step 7: Programming the Device and Verifying the Hardware topic completely to include more steps about how to program the device.
  • In Step 8: Verifying Hardware with Signal Tap , updated the Waveform after Signal Tap Analysis image.
  • In Step 5: Programming the Device and Verifying the Hardware, updated step 2 LEDs.
  • In Step 6: Verifying Hardware with Signal Tap , updated the Captured Data in Waveform Tab image.
  • In Step 8: Verifying the Hardware with Signal Tap , updated the Waveforms for Root Partition Nodes in Developer Project image. image.
  • In Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region, updated step 6 and 7 values.
  • In Step 4: Generating HDL Instance of Signal Tap, updated the image Signal Tap Logic Analyzer Intel FPGA IP Parameter Editor.
  • In Step 6: Programming the Device and Verifying the Hardware, updated step 2 LEDs.
  • In Step 4: Programming the Device and Verifying the Hardware, updated step 2 LEDs.
  • In Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap , updated the Waveforms for reserved core Partition Nodes in Consumer Project image.
  • In Step 6: Verifying Hardware of Root Partition with Signal Tap , updated the Waveforms for Root Partition Nodes in Consumer Project.
2019.09.11 19.1 Minor bug fix in Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition and Step 3: Generating and Instantiating the SLD JTAG Bridge Host topics.
2019.06.11 19.1
  • All occurrences of 'Periphery Reuse Core' partitions changed to 'Reserved Core' partitions.
  • Changed the convention of Intel® Quartus® Prime user guide titles.
  • Removed all inline icons and replaced it with menu options where applicable.
  • Updated all waveform images.
  • In Step 1: Creating a Core Partition, changed 'Set as Design Partition' to ' Default' and added note. Associated image was also updated.
  • Updated Step 4: Exporting the Core Partition and Creating the Black Box File to map to the GUI.
  • In Step 3: Creating a Partition for blinking_led_top, updated steps 1 and 2 images. Also changed 'Set as Design Partition' to ' Default' and added a note in step 1.
  • In Step 1: Creating a Reserved Core Partition and Defining a Region, updated step 3 to use Reserved Core design partition type. Updated the relevant image and removed the step about setting the core partition type.
  • In Step 3: Synthesizing, Creating File, and Compiling, added a new step 2 and an important note.
  • Updated the design example.
2018.05.07 18.0.0 Initial release.
Level Two Title