AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Public
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3.4. Step 4: Compiling the Design and Verifying Debug Nodes

After creating Signal Tap files for the parent and blinking_led_top partitions, you are ready to run a full compilation of the design. Then, verify the debug nodes connection.
  1. Click Compile Design on the Compilation Dashboard.
  2. In the Compilation Report, under Synthesis, view the In-System Debugging > Connections to In-System Debugging Instance “auto_signaltap_0” report to verify the connection of the ports.

    In the report, the Status column shows the connected debug ports.