AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition

Exporting the root partition in the Developer project does not include logic inside the reserved core or the SLD JTAG Bridge Host. The Consumer must add the SLD JTAG Bridge Host to the reserved core in the Consumer project.
  1. From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Host Intel® FPGA IP . Set the name as debug_host.
  2. Open the file, uncomment lines 26 to 31 and 48 to 55, and save the file.