AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

2.3. Step 3: Compiling and Checking Debug Nodes

  1. Click Compile Design on the Compilation Dashboard.
    Figure 13. Full Compilation in Compilation Dashboard
  2. Open the compilation report by clicking Processing > Compilation Report.
  3. Under Table of Contents, find Synthesis > In-System Debugging > Create Partition Boundary Ports.
    Figure 14. Create Partition Boundary Ports