AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

1.3. Signal Tap with Core Partition Reuse

To perform verification in a reusable core partition, in the Developer project, you must identify the signals of interest, and then make those signals visible to a Signal Tap logic analyzer instance. The Intel® Quartus® Prime software supports two methods of making core partition signals visible for verification:
  • Signal Tap HDL instanceIn the Developer project, you create a Signal Tap HDL instance in the reusable core partition and connect the signals of interest to that instance. The Compiler ensures top level visibility of Signal Tap instances inside partitions. Since the root partition and the core partition have separate HDL instances, the Signal Tap files are also separate.

    The Consumer must generate one Signal Tap file for each HDL instance present in the design.

  • Partition boundary ports—In this method, the Developer directly assigns signals as ports to the partition boundary. The top level partition contains an instance of Signal Tap, and signals in the partition boundary connect to it. Assigning boundary ports simplifies the management of hierarchical blocks, by automatically creating ports and tunneling through layers of logic, without making RTL changes. You create partition boundary ports through an Intel® Quartus® Prime Settings File (.qsf) assignment, or with the Assignment Editor.

    The Developer must include the user created partition boundary ports in the black box file. This action allows the Consumer to tap these ports as pre-synthesis or post-fit nodes.

Figure 3. Consumer Debug Setup with Reused Core Partition

The Consumer can add the Signal Tap logic analyzer to the parent partition with any of these methods:

  • Signal Tap HDL instance
  • Signal Tap GUI to tap pre-synthesis nodes
  • Signal Tap GUI to tap post-fit nodes

In this core partition reuse tutorial, the Developer creates partition boundary ports with the Assignment Editor, and the Consumer adds pre-synthesis nodes to the parent partition with the Signal Tap GUI. The following figure describes the Developer and Consumer flows:

Figure 4. Tutorial Design Flow for Core Partition Reuse