AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

5.1. Step 1: Adding Files to Customer Project

You import the timing constraints and the root partition database from the Developer project.
  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project, and open the a10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Consumer/top.qpf project file.
  2. Click Project > Add/Remove Files in Project.
  3. On the Files pane, click the browse (...) button next to the File name field to locate and select the top.sdc file, and click Add.
  4. Click Apply, and then click OK.
  5. If the Design Partitions Window is not visible, click Assignments > Design Partitions Window.
  6. In the Design Partitions Window, locate the root partition row, double-click the Partition Database File field, and then click browse (...).
  7. Select the root_partition.qdb file copied over from the Developer project.
  8. Click the partition name to confirm the .qdb assignment.