AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

3. Core Partition Reuse Debug—Consumer

In this tutorial, the Consumer receives a final core partition with boundary ports that correspond to signals useful for debugging. The Consumer adds the black box file and assigns the .qdb in the Consumer project. Then, the Consumer debugs the parent and reused core partition with a Signal Tap HDL instance, tapping partition boundary ports as pre-synthesis nodes.

Because the exported .qdb includes compiled netlist information, the Consumer project must target the same FPGA device part number, and use the same Intel® Quartus® Prime version as the Developer project.

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.

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