AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap

  1. Go to the shell from where you opened the Intel® Quartus® Prime software.
  2. In the shell, go to directory a10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Consumer , and then run the following command:
    quartus_stp top --create_signaltap_hdl_file --stp_file \
  3. In the Signal Tap window, click File > Open, and open the stp_root_partition.stp file, which you created in the previous step.
  4. Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
  5. Verify that Bridge Index is set to None in the JTAG Chain Configuration window
  6. To set the trigger condition, select the count[0], count[1], count[2], and count[3] signals, right-click the column under Trigger Conditions, and select Falling Edge.
  7. Run analysis by clicking Processing > Run Analysis.
    When the analysis finishes, the Waveform tab shows the captured data.
  8. Verify the transition of the nodes in the root partition.
    Figure 45. Waveforms for Root Partition Nodes in Consumer Project

In this tutorial design, the count[3:0] signals represent the counter in the root partition, and the top_LED signals represent the green LEDs on the board, which also map to the top-level (root) design. After the trigger activates, only one of the top_LED bits is low, at any time.

If the implementation succeeds, the Consumer project behaves identically to the Developer project.