AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683783
Date 7/26/2019
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1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

Updated for:
Intel® Quartus® Prime Design Suite 19.2
This tutorial demonstrates how to reuse design blocks in Intel® Quartus® Prime Pro Edition projects. The Intel® Quartus® Prime Pro Edition software supports block-based design flows, also known as modular or hierarchical design flows. These flows enable preservation of design blocks (or logic that comprises a hierarchical design instance) within a project, as well as reuse of design blocks in other projects.

You can reuse design blocks with the same periphery interface, share a synthesized design block with another designer, or replicate placed and routed IP in another project. Design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device. In design block reuse flows, you assign a hierarchical instance of logic as a design partition. You can then preserve, export, and reuse the partition according to the following reuse flows:

  • Core Partition Reuse—allows reuse of a synthesized or final snapshot of a core logic design partition (LUTs, flip-flops, M20K memory, and DSP blocks) in another project.
  • Root Partition Reuse—allows reuse of the synthesized or final snapshot of the root partition. The root partition includes periphery resources (including I/O, HSSIO, PCIe, PLLs), as well as any associated core resources, while reserving a region for subsequent development.