AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683783
Date 7/26/2019
Document Table of Contents

1.5. Core Partition Reuse—Consumer Tutorial

Follow the steps in this tutorial module to reuse a core partition in a Consumer project.

Process Description

As a core partition Consumer, you receive the final core partition that the Developer provides. The Consumer adds the black box file and assigns the .qdb in the Consumer project. Because the exported .qdb includes compiled netlist information, the Consumer project must target the same FPGA device part number, and use the same Intel® Quartus® Prime version as the Developer project.

Figure 11. File Exchange Between Developer and Consumer

The Consumer must specify all signals and port directions, as well as any Verilog HDL parameters or VHDL generics. The Developer can optionally include an .sdc for the partition to verify the partition timing results after full integration in the Consumer project.

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.

Command-Line Alternative Step

You can skip Step 1: Add Files and Run Synthesis through Step 3: Compile the Design in this tutorial module by adding following lines to the .qsf, and then running the Core_Partition_Reuse/Consumer/Script/ script:

#Create the partition
set_instance_assignment -name PARTITION blinking_led \
     -to u_blinking_led -entity top
#Assign the .qdb file to the partition
set_instance_assignment -name QDB_FILE_PARTITION blinking_led.qdb \
     -to u_blinking_led -entity top
#Add the BB file to the file list
set_global_assignment -name SYSTEMVERILOG_FILE