Visible to Intel only — GUID: yua1515009590848
Ixiasoft
Visible to Intel only — GUID: yua1515009590848
Ixiasoft
1.4.5. Step 5: Hardware Verification (Optional)
You can now optionally verify the results of the Core Partition Reuse—Developer tutorial module in hardware by completing (Optional) Step 8: Device Programming.
After completing this tutorial module, LEDs D6-D3 map to the blinking_led core, and LEDs D10-D7 map to the top-level design. After you configure the FPGA with the SRAM Object File (.sof), the blinking_led core flashes red LEDs in a binary counting order. The top-level design does not illuminate any LEDs.
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