AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683783
Date 7/26/2019
Document Table of Contents

1.4.5. Step 5: Hardware Verification (Optional)

You can now optionally verify the results of the Core Partition Reuse—Developer tutorial module in hardware by completing (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D6-D3 map to the blinking_led core, and LEDs D10-D7 map to the top-level design. After you configure the FPGA with the SRAM Object File (.sof), the blinking_led core flashes red LEDs in a binary counting order. The top-level design does not illuminate any LEDs.

Figure 10. Illumination of LEDs After Core Partition Reuse—Developer Tutorial Module