AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683783
Date 7/26/2019
Public
Document Table of Contents

1.4.3. Step 3: Create the Black Box File

Integrating a core partition .qdb into another project requires that you add a supporting black box file to the Consumer project. The black box file defines the ports and port interface types for the block that you reuse in the Consumer project. Follow these steps to create a black box port definitions file for the blinking_led partition.
  1. To create a new text file, click File > New, select SystemVerilog HDL File under Design Files, and then click OK. Create a file that contains only the port definitions for the partition you export. These are the same port definitions that the blinking_led.sv file specifies:
    module blinking_led (
        output [3:0] value,
        input      clock
        );
    
    endmodule
  2. Save the black box file as blinking_led_bb.sv. When saving this file, disable the option to Add file to current project.
    Figure 9. Disable Add File to Current Project

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