AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683783
Date 7/26/2019
Document Table of Contents

1.6.4. Step 4: Copy Files to Consumer Project

Manually copy the root_partition.qdb and top.sdc files to the Root_Partition_Reuse/Consumer/ directory.

Note: The top-level design requires .sdc constraints. The Consumer can also include a separate .sdc file to constrain the logic that they provide. The Logic Lock boundary is visible in the Chip Planner in the Consumer project for reference only. The Consumer cannot modify this region.

In the Root Partition Reuse—Consumer Tutorial, you integrate the root_partition.qdb and top.sdc files into the Consumer project.