AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683783
Date 7/26/2019
Document Table of Contents

1.6.5. Step 5: Hardware Verification (Optional)

You can now verify the results of the Root Partition Reuse—Developer Tutorial module in hardware by completing the steps in (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D6-D3 map to the blinking_led core, and LEDs D10-D7 map to the top-level (root) design. When you create and load the .sof, the blinking_led core does not illuminate any LEDs. The top-level design shows a shifting bit in green.

The behavior of the periphery LED driver carries into the Consumer project via the final .qdb file.

Figure 19. Illumination of LEDs after the Root Partition Reuse—Developer Tutorial

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