AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683783
Date 7/26/2019
Document Table of Contents
Give Feedback

1.4.1. Step 1: Define a Core Partition

Follow these steps to open the top.qpf tutorial project in the Intel® Quartus® Prime Pro Edition software, run design synthesis, and define a design partition for core logic.
  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open the /Core_Partition_Reuse/Developer/top.qpf project file.
  2. To synthesize the design, click Analysis & Synthesis on the Compilation Dashboard. The Compilation dashboard displays a check mark when synthesis is complete.
    Figure 4. Compilation Dashboard
  3. In the Project Navigator, right-click u_blinking_led in the Hierarchy tab, point to Design Partition, and select the Default partition Type. A design partition icon appears next to each instance you assign.
    Figure 5. Set as Design Partition
  4. To view and edit all design partitions in the project, click Assignments > Design Partitions Window. You can also define new partitions in this window, or specify automatic export of a partition following compilation.
    Figure 6. Design Partitions Window