AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683783
Date 7/26/2019
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Document Table of Contents x
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.6.1. Step 1: Create a Reserved Core Partition

To export and reuse the root partition, first create a reserved core partition for subsequent core logic development in the Consumer project. When you define the partition, you can optionally specify settings to automatically export the partition each time you run compilation.
  1. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open the /Root_Partition_Reuse/Developer/top.qpf project file.
  2. To synthesize the design, click Analysis & Synthesis on the Compilation Dashboard.
  3. In the Project Navigator, right-click u_blinking_led in the Hierarchy tab, point to Design Partition, and select the Reserved Core partition Type.
  4. To automatically export the final root_partition each time you run the Fitter, click Assignments > Design Partitions Window.
  5. Specify a .qdb file name for the Post Final Export File option for the partition. The .qdb exports to the directory you specify, or to the project directory by default.
    Figure 17. Setting Reserved Core Partition and Post Final Export File
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