AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

Download PDF
ID 683783
Date 7/26/2019
Public
Document Table of Contents
Document Table of Contents x
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.8. (Optional) Step 8: Device Programming

You can optionally configure the FPGA on the Intel® Arria® 10 GX Development Kit to verify the results in hardware. You can adapt the following steps if you are using a different device or development kit.
Configuring the FPGA involves opening the Intel® Quartus® Prime Pro Edition Programmer, connecting to the Development Kit board, and loading the configuration SRAM Object File (.sof) into the SRAM of the FPGA.
Note: A .sof file configures the SRAM of an Intel® FPGA. A Programmer Object File (.pof) programs a flash memory device with an FPGA configuration image for subsequent loading to an FPGA.

Follow these steps to configure the FPGA on the Intel® Arria® 10 GX Development Kit:

  1. To open the Intel® Quartus® Prime Programmer, click Tools > Programmer.
  2. Connect the board cables:
    • JTAG USB cable to board
    • Power cable attached to board and power source
  3. Turn on power to the board.
  4. In the Intel® Quartus® Prime Programmer, click Hardware Setup.
    Figure 26. Hardware Setup
  5. In the Hardware list, select USB-BlasterII, and then click Close. The device chain appears.
    Note: If the device chain does not appear, verify the board connections.
  6. Click Auto-Detect. The device chain populates.
  7. In the Found Devices list, select the device that matches your design and click OK. For this tutorial, select the 10AX115S2 device that matches the 10AX115S2F45I1SG FPGA on the Intel® Arria® 10 GX Development Kit.
    Figure 27. Select Device
  8. Right-click the 10AX115S2 row in the file list, and then click Change File.
    Figure 28. Programmer Window
  9. Browse to select the top.sof file from the appropriate tutorial/output_files/ directory.
  10. Enable the Program/Configure option for the 10AX115S2 row.
    Figure 29. Program/Configure Option
  11. Click Start. The progress bar reaches 100% when device configuration is complete. The device is now fully configured and in operation.
    Figure 30. Programming Successful
    Note: If device configuration fails, make sure the device you select for configuration matches the device you specify during .sof file generation.
Level Two Title