AN 985: Nios® V Processor Tutorial

ID 784468
Date 8/18/2023
Document Table of Contents
Give Feedback Starting the Debugger

  1. In the Run menu tab, select Debug Configurations.
  2. Under Ashling RISC-V Hardware Debugging, ELF_download is found (Create in 4.2 Download Software ELF File).
  3. Select ELF_download to start the Debugger using the same settings.
    Figure 46. Debug Configuration
  4. In the Main tab, check the following settings
    1. Project: app
    2. C/C++ Application: <Working directory>/software/app/build/Debug/hello.elf
  5. In the Debugger tab, check the following settings,
    1. Debug Probe Configuration,
      1. Debug probe: Intel Agilex development kit
      2. Transport type: JTAG
      3. JTAG frequency: 16 MHz
    2. Target Configuration: Click Auto-detect Scan Chain to list all possible cores. Select the appropriate Device/TAP and Nios V Processor Core.
    Figure 47. Main Tab
    Figure 48. Debugger Tab
  6. Click Apply and Debug.
  7. The Ashling* RiscFree* IDE for Intel® FPGAs switches to the Debug Perspective.
  8. The program begins execution, and suspends at the initial breakpoint, main().
    Figure 49. Suspended at Initial Breakpoint