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1.2.2.1.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.2.1.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP
1.2.2.1.3. Adding JTAG UART Intel® FPGA IP
1.2.2.1.4. Adding Reset Release Intel® FPGA IP
1.2.2.1.5. Connect Interfaces and Signals
1.2.2.1.6. Clear System Warnings and Errors
1.2.2.1.7. Configuring the Reset Vector of the Nios® V Processor
1.2.2.1.8. Saving and Generating System HDL
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1.4. Programming the System
Use the Quartus® Prime Programmer tool and the Ashling* RiscFree* IDE for Intel® FPGAs to program the Nios® V processor-based system into the FPGA and to run your application.