2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
2.5.1.2. Starting the Debugger
- In the Run menu tab, select Debug Configurations.
- Under Ashling RISC-V Hardware Debugging, find ELF_download (Created in Downloading Software ELF File.
- Select ELF_download to start the Debugger using the same settings.
Figure 89. Debug Configuration
- In the Main tab, check the following settings
- Project: app
- C/C++ Application: <Working directory>/software/app/build/Debug/hello.elf
- In the Debugger tab, check the following settings:
- For Debug Probe Configuration,
- Debug probe: Agilex™ development kit
- Transport type: JTAG
- JTAG frequency: 16 MHz
- Target Configuration: Click Auto-detect Scan Chain to list all possible cores. Select the appropriate Device/TAP and Nios V Processor Core.
Figure 90. Main TabFigure 91. Debugger Tab - For Debug Probe Configuration,
- Click Apply and Debug.
- The Ashling* RiscFree* IDE for Altera® FPGAs switches to the Debug Perspective.
- The program begins execution, and suspends at the initial breakpoint, main().
Figure 92. Suspended at Initial Breakpoint