22.214.171.124.1. Adding Nios® V/m Processor Intel® FPGA IP 126.96.36.199.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 188.8.131.52.3. Adding JTAG UART Intel® FPGA IP 184.108.40.206.4. Adding Reset Release Intel® FPGA IP 220.127.116.11.5. Connect Interfaces and Signals 18.104.22.168.6. Clear System Warnings and Errors 22.214.171.124.7. Configuring the Reset Vector of the Nios® V Processor 126.96.36.199.8. Saving and Generating System HDL
1.2.2. Building Hardware Design in Platform Designer
Begin designing the system hardware by instantiating the Nios® V processor and its peripherals into Platform Designer. After configuring the system assignments and constraints, complete the hardware design by performing a successful compilation.