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1.2.1.1.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.1.2.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP
1.2.1.1.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.1.2.4. Adding Reset Release Intel® FPGA IP
1.2.1.1.2.5. Connect Interfaces and Signals
1.2.1.1.2.6. Clear System Warnings and Errors
1.2.1.1.2.7. Configuring the Reset Vector of the Nios® V Processor
1.2.1.1.2.8. Saving and Generating System HDL
1.2.1.2.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.2.2.2. Adding On-Chip Memory (RAM or ROM) Intel® FPGA IP
1.2.1.2.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.2.2.4. Adding System ID Peripheral Intel® FPGA IP
1.2.1.2.2.5. Adding Reset Release Intel FPGA IP
1.2.1.2.2.6. Connect Interfaces and Signals
1.2.1.2.2.7. Clear System Warnings and Errors
1.2.1.2.2.8. Saving and Generating System HDL
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1.2.1. Building Hardware Design in Platform Designer
Begin designing the system hardware by instantiating the Nios® V processor and its peripherals into Platform Designer. After configuring the system assignments and constraints, complete the hardware design by performing a successful compilation.
Components | Description |
---|---|
Nios® V/m Processor Intel® FPGA IP | Runs application by executing instructions. |
JTAG UART Intel® FPGA IP | Enables serial character communication between Nios® V/m processor and host computer |
On-Chip Memory II Intel® FPGA IP | Stores data and instructions. |
Reset Release Intel® FPGA IP | Recommended reset output in SDM-based devices. |
You can design the system hardware by using one of the following methods:
- Manual instantiation
- Board-aware flow
- Configurable example design