AN 985: Nios® V Processor Tutorial

ID 784468
Date 7/24/2024
Public
Document Table of Contents

1.2.1. Building Hardware Design in Platform Designer

Begin designing the system hardware by instantiating the Nios® V processor and its peripherals into Platform Designer. After configuring the system assignments and constraints, complete the hardware design by performing a successful compilation.
Component Description
Components Description
Nios® V/m Processor Intel® FPGA IP Runs application by executing instructions.
JTAG UART Intel® FPGA IP Enables serial character communication between Nios® V/m processor and host computer
On-Chip Memory II Intel® FPGA IP Stores data and instructions.
Reset Release Intel® FPGA IP Recommended reset output in SDM-based devices.
You can design the system hardware by using one of the following methods:
  • Manual instantiation
  • Board-aware flow
  • Configurable example design