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1.2.2.1.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.2.1.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP
1.2.2.1.3. Adding JTAG UART Intel® FPGA IP
1.2.2.1.4. Adding Reset Release Intel® FPGA IP
1.2.2.1.5. Connect Interfaces and Signals
1.2.2.1.6. Clear System Warnings and Errors
1.2.2.1.7. Configuring the Reset Vector of the Nios® V Processor
1.2.2.1.8. Saving and Generating System HDL
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1.1.1. Hardware and Software Requirements
Hardware Requirements
- Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit ((DK-SI-AGF014EA)
- Power adapter
- Intel FPGA Download Cable II
Software Requirements
- Quartus® Prime Pro Edition Software version 23.2
- Ashling* RiscFree* IDE for Intel® FPGAs
- Questa* Intel® FPGA Edition
Note: You need to acquire the license for the Nios® V processor to compile the design in Quartus® Prime software.
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