Questa* Intel® FPGA Edition Quick-Start: Intel® Quartus® Prime Standard Edition

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ID 703090
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Questa* Intel® FPGA Edition Simulation Quick-Start ( Intel® Quartus® Prime Standard Edition) 2. Known Differences Between the Questa* Intel® FPGA Edition and ModelSim* - Intel® FPGA Edition 3. Questa* Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Standard Edition Revision History
1. Questa* Intel® FPGA Edition Simulation Quick-Start ( Intel® Quartus® Prime Standard Edition) x
1.1. Prerequisites 1.2. Open the Example Design 1.3. Specify EDA Tool Settings 1.4. Launch Simulation 1.5. View Signal Waveforms 1.6. Add Signals to the Simulation 1.7. Rerun Simulation
1. Questa* Intel® FPGA Edition Simulation Quick-Start ( Intel® Quartus® Prime Standard Edition)
2. Known Differences Between the Questa* Intel® FPGA Edition and ModelSim* - Intel® FPGA Edition
3. Questa* Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Standard Edition Revision History

1. Questa* Intel® FPGA Edition Simulation Quick-Start ( Intel® Quartus® Prime Standard Edition)

Updated for:
Intel® Quartus® Prime Design Suite 21.1
This document demonstrates how to simulate an Intel® Quartus® Prime Standard Edition design in the Questa* Intel® FPGA Edition simulator.
Note: This document intentionally uses basic features to accommodate requirements to simulate the design example mentioned in Open the Example Design. If you intend to use a different use case with advanced features and you need more information to simulate your design, then refer to the Questa* Intel® FPGA Edition documents from Siemens* available in the <installation directory>/questa_fe/docs/pdf_docs directory.

Design simulation verifies your design before device programming. It involves generating simulation files, compiling simulation models, running the simulation, and viewing the results. The following steps describe this flow in detail:

  1. Prerequisites
    Both Questa* Intel® FPGA Edition and Questa* Intel® FPGA Starter Edition software require valid software licenses. However, the Questa* Intel® FPGA Starter Edition license is free.
  2. Open the Example Design
    The PLL_RAM example design includes Intel® FPGA IP cores to demonstrate the basic simulation flow. Perform the following steps to open the design example:
  3. Specify EDA Tool Settings
    Perform the following steps to specify EDA Tool Options and generate simulation files for the supported simulators:
  4. Launch Simulation
    To generate and run Questa* Intel® FPGA Edition automation script from within the Intel® Quartus® Prime Standard Edition software, follow these steps:
  5. View Signal Waveforms
    Follow these steps to view signals in the testbench_1.v simulation waveform:
  6. Add Signals to the Simulation
    The CLOCK, WE, OFFSET, RESET_N, and RD_DATA signals automatically appear in the Wave window because the top-level design defines these I/O. In addition, you can optionally add internal signals to the simulation.
  7. Rerun Simulation
    You must rerun the simulation if you make changes to the simulation setup, such as adding signals to the Wave window, or modifying the testbench_1.v file. Follow these steps to rerun simulation:
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