AN 985: Nios® V Processor Tutorial

ID 784468
Date 8/28/2025
Public
Document Table of Contents

3.4.1. Programming Hardware SOF File

  1. Connect the MAX® 10 FPGA 10M50 Evaluation Kit to the host PC using the USB Blaster II.
  2. Open the Quartus® Prime Programmer.
    Figure 133.  Quartus® Prime Programmer
  3. Click Hardware Setup.
  4. Check the availability of the development kit in Available hardware items.
    1. If available, select the development kit in Currently selected hardware.
    2. If not available, check the cable connection, and the JtagServer driver installation.
    Figure 134. Hardware Setup
  5. Click Auto Detect and select the appropriate device OPN.
  6. Select the MAX® 10 device, click Change File and select niosv_top.sof file.
  7. Once the SOF file is ready, check Program/Configure and click Start.
    Figure 135. List of Devices with JTAG Chain
  8. Wait until the Progress bar reaches 100% (Successful).
    Figure 136. Progress Bar
  9. You have successfully configured the development kit with the processor hardware system.

    Alternatively, you can program the hardware SOF file through CLI.

    Execute the following command to program the SOF file.

    $ quartus_pgm -c 1 -m JTAG -o p;<Working directory>/output_files/niosv_top.sof@1