AN 985: Nios® V Processor Tutorial

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ID 784468
Date 5/15/2024
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Document Table of Contents
Document Table of Contents x
1. AN 985: Nios® V Processor Tutorial
1. AN 985: Nios® V Processor Tutorial x
1.1. Overview 1.2. Generating the System 1.3. Simulating the Nios® V Processor System 1.4. Programming the System 1.5. Debugging the System 1.6. Document Revision History for AN 985: Nios® V Processor Tutorial
1.1. Overview x
1.1.1. Hardware and Software Requirements
1.2. Generating the System x
1.2.1. Creating a New Project 1.2.2. Building Hardware Design in Platform Designer 1.2.3. Building Software Design with Ashling* RiscFree* IDE for Intel® FPGAs
1.2.2. Building Hardware Design in Platform Designer x
1.2.2.1. Creating a Platform Designer System 1.2.2.2. Configuring Assignment and Constraint 1.2.2.3. Compiling the Quartus® Prime Software Project
1.2.2.1. Creating a Platform Designer System x
1.2.2.1.1. Adding Nios® V/m Processor Intel® FPGA IP 1.2.2.1.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 1.2.2.1.3. Adding JTAG UART Intel® FPGA IP 1.2.2.1.4. Adding Reset Release Intel® FPGA IP 1.2.2.1.5. Connect Interfaces and Signals 1.2.2.1.6. Clear System Warnings and Errors 1.2.2.1.7. Configuring the Reset Vector of the Nios® V Processor 1.2.2.1.8. Saving and Generating System HDL
1.2.2.2. Configuring Assignment and Constraint x
1.2.2.2.1. Adding Design Files 1.2.2.2.2. Adding Synopsys Design Constraint (SDC) File 1.2.2.2.3. Pin Assignments 1.2.2.2.4. Configuration and Power Management Assignments
1.2.3. Building Software Design with Ashling* RiscFree* IDE for Intel® FPGAs x
1.2.3.1. Creating a Board Support Package 1.2.3.2. Creating an Application Project File 1.2.3.3. Importing Projects into Ashling* RiscFree* IDE for Intel® FPGAs 1.2.3.4. Building the Hello World Application
1.2.3.3. Importing Projects into Ashling* RiscFree* IDE for Intel® FPGAs x
1.2.3.3.1. Importing Nios® V Processor BSP Project 1.2.3.3.2. Importing Application Project
1.3. Simulating the Nios® V Processor System x
1.3.1. Preparing Hardware Design for Simulation 1.3.2. Preparing Software Design for Simulation 1.3.3. Checking Simulation Files 1.3.4. Running System Simulation
1.4. Programming the System x
1.4.1. Programming Hardware SOF File 1.4.2. Downloading the Software ELF File 1.4.3. Applying External Tool Configuration 1.4.4. Run Hello World Application
1.5. Debugging the System x
1.5.1. Software Debugging
1.5.1. Software Debugging x
1.5.1.1. Setting Initial Breakpoint 1.5.1.2. Starting the Debugger 1.5.1.3. View Global Variables 1.5.1.4. View Memory 1.5.1.5. Setting a Second Breakpoint 1.5.1.6. Control Debugger
1. AN 985: Nios® V Processor Tutorial

1.4.3. Applying External Tool Configuration

External tool configuration is a generic feature where you can configure the Ashling* RiscFree* IDE for Intel® FPGAs to include external tools. An example of such tools is the juart-terminal executable, which is used to display the Hello World message through the JTAG UART IP.

To perform external tool configuration for juart-terminal, follow these steps:

  1. Go to Run > External Tools > External Tools Configurations.
  2. Double click Program to open a New_configuration window.
  3. Rename the configuration as Nios V JTAG UART Output.
  4. In Location, click Browse File system.
  5. Browse and select the juart-terminal file in the following paths:
    Table 3.  Path
    Operating System Path
    Windows* <Intel Quartus Prime installation directory>/quartus/bin64/juart-terminal.exe
    Linux* <Intel Quartus Prime installation directory>/quartus/linux64/juart-terminal
  6. Set the Arguments as “-c 1 -d 0 -i 0”. This configures the JTAG UART connection is towards the JTAG UART IP at cable 1, device 0 and instance 0.
  7. Click Apply.
Note: JTAG device chain index varies according to your setup. To obtain the latest device chain index numbering, run openocd-cfg-gen –print command in Nios® V Command Shell.
Figure 43. External Tools Configuration
Level Two Title