18.104.22.168.1. Adding Nios® V/m Processor Intel® FPGA IP 22.214.171.124.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 126.96.36.199.3. Adding JTAG UART Intel® FPGA IP 188.8.131.52.4. Adding Reset Release Intel® FPGA IP 184.108.40.206.5. Connect Interfaces and Signals 220.127.116.11.6. Clear System Warnings and Errors 18.104.22.168.7. Configuring the Reset Vector of the Nios® V Processor 22.214.171.124.8. Saving and Generating System HDL
1.3.4. Running System Simulation
The msim_setup.tcl script in the package generated creates alias commands for each step. For the list of commands, refer to the following table:
|dev_com||Compile device library files.|
|com||Compiles the design files in correct order.|
|elab||Elaborates the top-level design.|
|elab_debug||Elaborates the top-level design with the novopt option.|
|ld||Compiles all the design files and elaborates the top-level design.|
Compiles all the design files and elaborates the top-level design with the vopt option.
Note: The vopt option is to run optimization before elaborating the top-level design in the simulator.
You can run the simulation in the Questa simulator by performing the following steps,
- Launch the Nios V Command Shell.
- Open the Questa for Intel FPGA simulator using the command vsim.
- In the Questa Transcript window, change your working directory to the mentor folder.
cd <Working directory>/niosv_top_tb/niosv_top_tb/sim/mentor
- Copy the memory initialization file into the mentor folder.
file copy -force \
<Working directory>/software/app/build/Debug/hello.hex ./
- Run the msim_setup.tcl.
- Compiles all the design files and elaborates the top-level design with vopt option.
- Run the simulation for more than 5 milliseconds.
At the end of the simulation, you can find the following message prints in the Questa Transcript window: Hello world, this is the Nios V/m cpu checking in <loop number>.
Figure 32. Questa Transcript Window Message
You can observe the simulation results from the waveform viewer:
- In Questa for Intel FPGA simulator, navigate to the Instance window.
- Unroll niosv_top_tb.
- Select niosv_top_inst, and the simulator populates a list of signals in the Objects window.
- Right-click any of the signals, and click Add Waves to add them into the Wave window.
- Restart and run the simulation for more than 5 milliseconds.
- Wait for the simulator to complete the given time.
Figure 33. Questa Instance and Objects Windows
The following figure shows the simulated wave result.
- 1st signal: Clock Input
- 2nd signal: Reset Input
- Other signals: Any one or more signals within the niosv_top_inst
Figure 34. Waveform Viewer