AN 985: Nios® V Processor Tutorial

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ID 784468
Date 8/18/2023
Public
Document Table of Contents
Document Table of Contents x
1. AN 985: Nios® V Processor Tutorial
1. AN 985: Nios® V Processor Tutorial x
1.1. Overview 1.2. Generating the System 1.3. Simulating the Nios® V Processor System 1.4. Programming the System 1.5. Debugging the System 1.6. Document Revision History for AN 985: Nios® V Processor Tutorial
1.1. Overview x
1.1.1. Hardware and Software Requirements
1.2. Generating the System x
1.2.1. Creating a New Project 1.2.2. Building Hardware Design in Platform Designer 1.2.3. Building Software Design with Ashling* RiscFree* IDE for Intel® FPGAs
1.2.2. Building Hardware Design in Platform Designer x
1.2.2.1. Creating a Platform Designer System 1.2.2.2. Configuring Assignment and Constraint 1.2.2.3. Compiling the Intel® Quartus® Prime Software Project
1.2.2.1. Creating a Platform Designer System x
1.2.2.1.1. Adding Nios® V/m Processor Intel® FPGA IP 1.2.2.1.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 1.2.2.1.3. Adding JTAG UART Intel® FPGA IP 1.2.2.1.4. Adding Reset Release Intel® FPGA IP 1.2.2.1.5. Connect Interfaces and Signals 1.2.2.1.6. Clear System Warnings and Errors 1.2.2.1.7. Configuring the Reset Vector of the Nios® V Processor 1.2.2.1.8. Saving and Generating System HDL
1.2.2.2. Configuring Assignment and Constraint x
1.2.2.2.1. Adding Design Files 1.2.2.2.2. Adding Synopsys Design Constraint (SDC) File 1.2.2.2.3. Pin Assignments 1.2.2.2.4. Configuration and Power Management Assignments
1.2.3. Building Software Design with Ashling* RiscFree* IDE for Intel® FPGAs x
1.2.3.1. Creating a Board Support Package 1.2.3.2. Creating an Application Project File 1.2.3.3. Importing Projects into Ashling* RiscFree* IDE for Intel® FPGAs 1.2.3.4. Building the Hello World Application
1.2.3.3. Importing Projects into Ashling* RiscFree* IDE for Intel® FPGAs x
1.2.3.3.1. Importing Nios® V Processor BSP Project 1.2.3.3.2. Importing Application Project
1.3. Simulating the Nios® V Processor System x
1.3.1. Preparing Hardware Design for Simulation 1.3.2. Preparing Software Design for Simulation 1.3.3. Checking Simulation Files 1.3.4. Running System Simulation
1.4. Programming the System x
1.4.1. Programming Hardware SOF File 1.4.2. Downloading the Software ELF File 1.4.3. Applying External Tool Configuration 1.4.4. Run Hello World Application
1.5. Debugging the System x
1.5.1. Software Debugging
1.5.1. Software Debugging x
1.5.1.1. Setting Initial Breakpoint 1.5.1.2. Starting the Debugger 1.5.1.3. View Global Variables 1.5.1.4. View Memory 1.5.1.5. Setting a Second Breakpoint 1.5.1.6. Control Debugger
1. AN 985: Nios® V Processor Tutorial

1.3.4. Running System Simulation

The msim_setup.tcl script in the package generated creates alias commands for each step. For the list of commands, refer to the following table:
Macros Description
dev_com Compile device library files.
com Compiles the design files in correct order.
elab Elaborates the top-level design.
elab_debug Elaborates the top-level design with the novopt option.
ld Compiles all the design files and elaborates the top-level design.
ld_debug
Compiles all the design files and elaborates the top-level design with the vopt option.
Note: The vopt option is to run optimization before elaborating the top-level design in the simulator.

You can run the simulation in the Questa simulator by performing the following steps,

  1. Launch the Nios V Command Shell.
  2. Open the Questa for Intel FPGA simulator using the command vsim.
  3. In the Questa Transcript window, change your working directory to the mentor folder.
    cd <Working directory>/niosv_top_tb/niosv_top_tb/sim/mentor
  4. Copy the memory initialization file into the mentor folder.
    file copy -force \
    <Working directory>/software/app/build/Debug/hello.hex ./
  5. Run the msim_setup.tcl. 
    do msim_setup.tcl
  6. Compiles all the design files and elaborates the top-level design with vopt option.
    ld_debug
  7. Run the simulation for more than 5 milliseconds. 
    run 10ms
At the end of the simulation, you can find the following message prints in the Questa Transcript window: Hello world, this is the Nios V/m cpu checking in <loop number>.
Figure 32. Questa Transcript Window Message

You can observe the simulation results from the waveform viewer:

  1. In Questa for Intel FPGA simulator, navigate to the Instance window.
  2. Unroll niosv_top_tb.
  3. Select niosv_top_inst, and the simulator populates a list of signals in the Objects window.
  4. Right-click any of the signals, and click Add Waves to add them into the Wave window.
  5. Restart and run the simulation for more than 5 milliseconds. 
    restart
    run 10ms
  6. Wait for the simulator to complete the given time.
Figure 33. Questa Instance and Objects Windows

The following figure shows the simulated wave result.

  • 1st signal: Clock Input
  • 2nd signal: Reset Input
  • Other signals: Any one or more signals within the niosv_top_inst
Figure 34. Waveform Viewer
Level Two Title