126.96.36.199.1. Adding Nios® V/m Processor Intel® FPGA IP 188.8.131.52.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 184.108.40.206.3. Adding JTAG UART Intel® FPGA IP 220.127.116.11.4. Adding Reset Release Intel® FPGA IP 18.104.22.168.5. Connect Interfaces and Signals 22.214.171.124.6. Clear System Warnings and Errors 126.96.36.199.7. Configuring the Reset Vector of the Nios® V Processor 188.8.131.52.8. Saving and Generating System HDL
1.3.3. Checking Simulation Files
At this point in the design flow, you have generated your system and created all the files necessary for simulation listed in the table below.
|<Working directory>/niosv_top_tb/*||Platform Designer generates a testbench system when you enable the Create testbench Platform Designer system option.|
|<Working directory>/niosv_top_tb/niosv_top_tb/sim/mentor/msim_setup.tcl||Sets up a Questa simulation environment and creates alias commands to compile the required device libraries and system design files in the correct order and loads the top-level design for simulation.|
|<Working directory>/software/app/build/Debug/hello.hex||Memory Initialization Files (.hex) is required to initialize memory components in your system.|