2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
2.2.2.3.1. Adding Design Files
- In Quartus® Prime software, navigate to Assignments menu bar and click Settings.
- Navigate to Files category. You can find all related IP files and QSYS file added into your project.
Figure 21. Settings – Files Category
- Earlier during the new project creation, the top-level design entity is named niosv_top. Thus, the niosv_top.qsys file is automatically the top-level design entity.
- Check the top-level design entity assignment in the Project Navigator.
Figure 22. Project Navigator