AN 985: Nios® V Processor Tutorial

ID 784468
Date 7/24/2024
Public

Visible to Intel only — GUID: rke1689657296314

Ixiasoft

Document Table of Contents

1.2.1.1.2.4. Adding Reset Release Intel® FPGA IP

  1. Search for Reset Release in the IP Catalog.
  2. Add the Reset Release Intel FPGA IP under Basic Functions > Configuration and Programming section. The New IP Variation window appears.
  3. Select the type of reset output port as Reset Interface.
  4. Click Finish to instantiate the peripheral.
    Figure 15. Reset Release IP Parameter Editor