AN 985: Nios® V Processor Tutorial

ID 784468
Date 8/18/2023
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1.4.2. Downloading the Software ELF File

  1. Ensure that the development kit is successfully configured with the processor system.
  2. Launch the Ashling* RiscFree* IDE for Intel® FPGAs.
  3. Navigate to Run > Run Configurations.
  4. In Run Configuration window, double click Ashling RISC-V Hardware Debugging and name it as ELF_download.
    Figure 39. Run Configuration
  5. In the Main tab, make the following settings:
    1. Project: app
    2. C/C++ Application: <Working directory>/software/app/build/Debug/hello.elf
    Figure 40. Main Tab
  6. In the Debugger tab, make the following settings:
    1. Debug Probe Configuration:
      1. Debug probe: Intel Agilex® development kit
      2. Transport type: JTAG
      3. JTAG frequency: 16 MHz
    2. Target Configuration: Click Auto-detect Scan Chain to list all possible cores. Select the appropriate Device/TAP and Nios V Processor Core.
    Figure 41. Debugger Tab
  7. Click Apply and Run. Ashling* RiscFree* IDE for Intel® FPGAs prints the following message in its Console.
    Figure 42. ELF_download Message (Console tab)