184.108.40.206.1. Adding Nios® V/m Processor Intel® FPGA IP 220.127.116.11.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 18.104.22.168.3. Adding JTAG UART Intel® FPGA IP 22.214.171.124.4. Adding Reset Release Intel® FPGA IP 126.96.36.199.5. Connect Interfaces and Signals 188.8.131.52.6. Clear System Warnings and Errors 184.108.40.206.7. Configuring the Reset Vector of the Nios® V Processor 220.127.116.11.8. Saving and Generating System HDL
18.104.22.168.1. Adding Design Files
- In Intel® Quartus® Prime software, navigate to Assignments menu bar and click Settings.
- Navigate to Files category. You can find all related IP files and QSYS file added into your project.
Figure 21. Settings – Files Category
- Earlier during the new project creation, the top-level design entity is named niosv_top. Thus, the niosv_top.qsys file is automatically the top-level design entity.
- Check the top-level design entity assignment in the Project Navigator.
Figure 22. Project Navigator
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