AN 985: Nios® V Processor Tutorial

ID 784468
Date 8/18/2023
Document Table of Contents

1.3.1. Preparing Hardware Design for Simulation

Note: Before continuing the simulation, you must successfully build the hardware SOF file (with the memory-initialization feature enabled).

To generate hardware simulation files, perform the following steps:

  1. Launch the Intel® Quartus® Prime software and open the Platform Designer from the Tools menu.
  2. Open the niosv_top.qsys file.
  3. In Platform Designer, navigate to Generate > Generate Testbench System.
  4. On the Generation window, set the following parameters to these values:
    1. Create testbench Platform Designer system— Standard, BFMs for standard Platform Designer interfaces.
    2. Create testbench simulation model—Verilog
    3. Turn on Use multiple processors for faster IP generation (when available).
  5. Click Generate, and Save, if prompted.
    Intel IP cores and Platform Designer systems generate simulation setup scripts. Modify these scripts to set up supported simulators. You can find the script, msim_setup.tcl in the following path:
    <Working directory>/niosv_top_tb/sim/mentor
    Figure 31. Testbench Generation

Did you find the information on this page useful?

Characters remaining:

Feedback Message