126.96.36.199.1. Adding Nios® V/m Processor Intel® FPGA IP 188.8.131.52.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 184.108.40.206.3. Adding JTAG UART Intel® FPGA IP 220.127.116.11.4. Adding Reset Release Intel® FPGA IP 18.104.22.168.5. Connect Interfaces and Signals 22.214.171.124.6. Clear System Warnings and Errors 126.96.36.199.7. Configuring the Reset Vector of the Nios® V Processor 188.8.131.52.8. Saving and Generating System HDL
184.108.40.206.4. Configuration and Power Management Assignments
- In Intel® Quartus® Prime software, navigate to Assignments menu bar and click Device > Device and Pin Options.
- Navigate to Configuration category.
- Select VID mode of operation as PMBus Master.
- Click Configuration Pin Options, and make the following Configuration pin assignments,
- PWRMGT_SCL as SDM_IO0
- PWRMGT_SDA as SDM_IO12
- CONF_DONE as SDM_IO16
- Leave the rest empty.
- Navigate to Power Management & VID category, and make the following settings
- Bus speed mode as 100 kHz
- Slave device type as Other
- PMBus device 0 slave address as 42
- Voltage output format as Linear format
- Linear format N as -13
- Translated voltage value unit as Volts
- Turn off PAGE command.
- Click OK, and return to the project front page.