AN 985: Nios® V Processor Tutorial

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ID 784468
Date 8/18/2023
Public
Document Table of Contents
Document Table of Contents x
1. AN 985: Nios® V Processor Tutorial
1. AN 985: Nios® V Processor Tutorial x
1.1. Overview 1.2. Generating the System 1.3. Simulating the Nios® V Processor System 1.4. Programming the System 1.5. Debugging the System 1.6. Document Revision History for AN 985: Nios® V Processor Tutorial
1.1. Overview x
1.1.1. Hardware and Software Requirements
1.2. Generating the System x
1.2.1. Creating a New Project 1.2.2. Building Hardware Design in Platform Designer 1.2.3. Building Software Design with Ashling* RiscFree* IDE for Intel® FPGAs
1.2.2. Building Hardware Design in Platform Designer x
1.2.2.1. Creating a Platform Designer System 1.2.2.2. Configuring Assignment and Constraint 1.2.2.3. Compiling the Intel® Quartus® Prime Software Project
1.2.2.1. Creating a Platform Designer System x
1.2.2.1.1. Adding Nios® V/m Processor Intel® FPGA IP 1.2.2.1.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP 1.2.2.1.3. Adding JTAG UART Intel® FPGA IP 1.2.2.1.4. Adding Reset Release Intel® FPGA IP 1.2.2.1.5. Connect Interfaces and Signals 1.2.2.1.6. Clear System Warnings and Errors 1.2.2.1.7. Configuring the Reset Vector of the Nios® V Processor 1.2.2.1.8. Saving and Generating System HDL
1.2.2.2. Configuring Assignment and Constraint x
1.2.2.2.1. Adding Design Files 1.2.2.2.2. Adding Synopsys Design Constraint (SDC) File 1.2.2.2.3. Pin Assignments 1.2.2.2.4. Configuration and Power Management Assignments
1.2.3. Building Software Design with Ashling* RiscFree* IDE for Intel® FPGAs x
1.2.3.1. Creating a Board Support Package 1.2.3.2. Creating an Application Project File 1.2.3.3. Importing Projects into Ashling* RiscFree* IDE for Intel® FPGAs 1.2.3.4. Building the Hello World Application
1.2.3.3. Importing Projects into Ashling* RiscFree* IDE for Intel® FPGAs x
1.2.3.3.1. Importing Nios® V Processor BSP Project 1.2.3.3.2. Importing Application Project
1.3. Simulating the Nios® V Processor System x
1.3.1. Preparing Hardware Design for Simulation 1.3.2. Preparing Software Design for Simulation 1.3.3. Checking Simulation Files 1.3.4. Running System Simulation
1.4. Programming the System x
1.4.1. Programming Hardware SOF File 1.4.2. Downloading the Software ELF File 1.4.3. Applying External Tool Configuration 1.4.4. Run Hello World Application
1.5. Debugging the System x
1.5.1. Software Debugging
1.5.1. Software Debugging x
1.5.1.1. Setting Initial Breakpoint 1.5.1.2. Starting the Debugger 1.5.1.3. View Global Variables 1.5.1.4. View Memory 1.5.1.5. Setting a Second Breakpoint 1.5.1.6. Control Debugger
1. AN 985: Nios® V Processor Tutorial

1.2.2.2.4. Configuration and Power Management Assignments

  1. In Intel® Quartus® Prime software, navigate to Assignments menu bar and click Device > Device and Pin Options.
  2. Navigate to Configuration category.
  3. Select VID mode of operation as PMBus Master.
  4. Click Configuration Pin Options, and make the following Configuration pin assignments,
    • PWRMGT_SCL as SDM_IO0
    • PWRMGT_SDA as SDM_IO12
    • CONF_DONE as SDM_IO16
    • Leave the rest empty.
  5. Navigate to Power Management & VID category, and make the following settings
    • Bus speed mode as 100 kHz
    • Slave device type as Other
    • PMBus device 0 slave address as 42
    • Voltage output format as Linear format
    • Linear format N as -13
    • Translated voltage value unit as Volts
    • Turn off PAGE command.
  6. Click OK, and return to the project front page.
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