Visible to Intel only — GUID: hls1689651616279
Ixiasoft
1.2.1.1.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.1.2.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP
1.2.1.1.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.1.2.4. Adding Reset Release Intel® FPGA IP
1.2.1.1.2.5. Connect Interfaces and Signals
1.2.1.1.2.6. Clear System Warnings and Errors
1.2.1.1.2.7. Configuring the Reset Vector of the Nios® V Processor
1.2.1.1.2.8. Saving and Generating System HDL
1.2.1.2.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.2.2.2. Adding On-Chip Memory (RAM or ROM) Intel® FPGA IP
1.2.1.2.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.2.2.4. Adding System ID Peripheral Intel® FPGA IP
1.2.1.2.2.5. Adding Reset Release Intel FPGA IP
1.2.1.2.2.6. Connect Interfaces and Signals
1.2.1.2.2.7. Clear System Warnings and Errors
1.2.1.2.2.8. Saving and Generating System HDL
Visible to Intel only — GUID: hls1689651616279
Ixiasoft
1.2.2.1.3. Adding JTAG UART Intel® FPGA IP
- Search for JTAG UART in the IP Catalog.
- Add the JTAG UART Intel FPGA IP under Interface Protocols > Serial section. The New IP Variation window appears.
- Click Finish to instantiate the peripheral. Leave it at the default settings.
Figure 14. JTAG UART IP Parameter Editor