Visible to Intel only — GUID: okf1689668882712
Ixiasoft
1.2.1.1.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.1.2.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP
1.2.1.1.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.1.2.4. Adding Reset Release Intel® FPGA IP
1.2.1.1.2.5. Connect Interfaces and Signals
1.2.1.1.2.6. Clear System Warnings and Errors
1.2.1.1.2.7. Configuring the Reset Vector of the Nios® V Processor
1.2.1.1.2.8. Saving and Generating System HDL
1.2.1.2.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.2.2.2. Adding On-Chip Memory (RAM or ROM) Intel® FPGA IP
1.2.1.2.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.2.2.4. Adding System ID Peripheral Intel® FPGA IP
1.2.1.2.2.5. Adding Reset Release Intel FPGA IP
1.2.1.2.2.6. Connect Interfaces and Signals
1.2.1.2.2.7. Clear System Warnings and Errors
1.2.1.2.2.8. Saving and Generating System HDL
Visible to Intel only — GUID: okf1689668882712
Ixiasoft
1.2.2.2.2. Adding Synopsys Design Constraint (SDC) File
- Click New, select Synopsys Design Constraint File and click OK.
- Add the following constraint:
create_clock -name clk -period 10.0 [get_ports clk_clk]
- Save as niosv_top.sdc.