2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
3.3.4. Running System Simulation
The msim_setup.tcl script in the package generated creates alias commands for each step. For the list of commands, refer to the following table:
Macros | Description |
---|---|
dev_com | Compile device library files. |
com | Compiles the design files in correct order. |
elab | Elaborates the top-level design. |
elab_debug | Elaborates the top-level design with the novopt option. |
ld | Compiles all the design files and elaborates the top-level design. |
ld_debug |
Compiles all the design files and elaborates the top-level design with the vopt option.
Note: The vopt option is to run optimization before elaborating the top-level design in the simulator.
|
You can run the simulation in the Questa simulator by performing the following steps,
- Launch the Nios V Command Shell.
- Open the Questa for Intel FPGA simulator using the command vsim.
- In the Questa Transcript window, change your working directory to the mentor folder.
cd <Working directory>/niosv_top_tb/niosv_top_tb/sim/mentor
- Copy the memory initialization file into the mentor folder.
file copy -force \ <Working directory>/software/app/build/Default/hello.hex ./
- Run the msim_setup.tcl.
do msim_setup.tcl
- Compiles all the design files and elaborates the top-level design with vopt option.
ld_debug
- Run the simulation for more than 5 milliseconds.
run 10ms
At the end of the simulation, you can find the following message prints in the Questa Transcript window: Hello world, this is the Nios V/m cpu checking in <loop number>.
Figure 75. Figure 130. Questa Transcript Window Message
You can observe the simulation results from the waveform viewer:
- In Questa for Intel FPGA simulator, navigate to the Instance window.
- Unroll niosv_top_tb.
- Select niosv_top_inst, and the simulator populates a list of signals in the Objects window.
- Right-click any of the signals, and click Add Waves to add them into the Wave window.
- Restart and run the simulation for more than 5 milliseconds.
restart
run 10ms
- Wait for the simulator to complete the given time.
Figure 76. Figure 131. Questa Instance and Objects Windows
The following figure shows the simulated wave result.
- First signal: Clock Input
- Second signal: Reset Input
- Other signals: Any one or more signals within the niosv_top_inst
Figure 77. Figure 132. Waveform Viewer