AN 985: Nios® V Processor Tutorial

ID 784468
Date 8/28/2025
Public
Document Table of Contents

3.2.1.3. Configuring Assignment and Constraint

Add Synopsys Design Constraint (SDC) File

  1. Click New, select Synopsys Design Constraint File and click OK.
  2. Add the following constraint:
    create_clock -name {altera_reserved_tck} -period 62.500 -waveform { 0.000 
    31.250 }[get_ports {altera_reserved_tck}]
    create_clock -name {clk} -period 20.0 [get_ports clk_clk]
    
    
    set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
  3. Save as niosv_top.sdc.

Adding Design Files

  1. In Quartus® Prime software, navigate to Assignments menu bar and click Settings.
  2. Navigate to Files category. Click Add All to add the QSYS file to your project.
  3. Click OK to exit the Settings window.
    Figure 117. Settings – Files Category
    Figure 118. Project Navigator

Configuration Mode

  1. In Quartus® Prime software, navigate to Assignments menu bar and click Device.
  2. Click Device and Options.
  3. Navigate to Configuration category, set the Configuration mode to Single Uncompressed Image with Memory Initialization.
    Figure 119. Configuration Mode
  4. Click OK to exit Device and Options window.
  5. Click OK to exit Device window.

Pin Assignment

  1. In Quartus® Prime software, navigate to Processing menu bar and click Start > Start Analysis & Elaboration.
  2. Once the analysis is complete, navigate to Assignments menu bar and click Pin Planner. For this example, there are 2 pins assignments:
    • clk_clk assigned to PIN_J10
    • reset_reset_n assigned to PIN_D9
  3. Close Pin Planner and return to the project front page.