2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
3.2.1.1. Creating a New Project
Start developing the Nios® V processor system by creating a new Quartus® Prime software.
- Launch Quartus Prime Standard Edition software.
- Click New Project Wizard to create a new project.
Figure 98. New Project Wizard
- Read the Introduction and click Next to proceed.
Figure 99. New Project Wizard—Introduction
- In Directory, Name, Top-Level Entity window, follow these steps:
- Enter your working directory, define the name of the project and enter the top-level design entity as niosv_top.
- Click Next to proceed.
Figure 100. Specifying the Properties of the Project - In Project Type window, select Empty Project and click Next.
Figure 101. Selecting Project Settings
- In Add Files window, leave it empty and click Next to proceed.
Figure 102. Add Files Window
- In Family, Device & Board Settings window, select the following values:
- Family: MAX10 (DA/DD/DF/DC/SA/SC/SL)
- Name filter: 10M50DAF484C6GES
Figure 103. Device Tab - In EDA Tool Settings window, select Questa IP. (This is for simulation in later chapter.)
Figure 104. EDA Tool Settings
- Click Next to review the summary of the new project. Then click Finish.
Figure 105. Summary