2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
3.5.1.4. View Memory
Ashling* RiscFree* IDE for Altera® FPGAs supports memory browser. You can view the content of On-Chip Memory (RAM) or other memory devices. This example targets the start address of On-Chip Memory (RAM), which the Hello World application begins.
To launch the memory browser, follow these steps:
- Go to Window > Show View > Memory Browser.
- Select Add Memory Monitor.
- Provide the memory address 0x0, and click OK.
Figure 94. Figure 149. Memory Browser at Address 0x0
- Go to <Working directory>/software/app/build/Debug folder.
- Open the hello.elf.objdump file.
- Search for Disassembly of section .entry.
- The disassembly shows that the information at starting address 0 is 0x36c006f, which is exactly the same as in the Memory Browser.
- You can continue to verify section .exceptions.
Figure 95. Figure 150. Disassembly of Hello World Application