2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
3.2.2.3.1. Importing Nios® V Processor BSP Project
Follow these steps to import the Nios® V processor BSP:
- Search Ashling* RiscFree* IDE for Altera® FPGAs in Start Menu and open it.
- Set the working directory as the Workspace.
- Open the Import wizard, click File > Import Nios V CMake Project.
- In the Import window, browse and select the location of the Nios® V processor BSP project.
- The Project name is automatically fill according to the name of BSP project.
- Click Finish. The BSP project is added to the Project Explorer.
Figure 126. Importing BSP Project into Ashling* RiscFree* IDE for Altera® FPGAs