2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
After the processor system is ready, you may begin building the software design using Ashling* RiscFree* IDE for Altera® FPGAs software. It consists of the following steps:
- Create a board support package (BSP) project.
- Create a Nios® V processor application project with Hello World source code.
- Import both projects into RiscFree IDE’s workspace.
- Build the Hello World application.
To ensure a streamlined build flow, you are encouraged to create similar directory tree in your design project. The following software design flow is based on this directory tree.
To create the software project directory tree, follow these steps:
- In your design project folder, create a folder called software.
- In the software folder, create two folders called app and bsp
Figure 66. Software Project Directory Tree