2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.5. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
2.2.2.2.1. Adding Nios® V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios® V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.3.2.1. Adding Nios® V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
3.2.2.2. Creating an Application Project Files
Application Project (app) provides the software application for Nios V/m processor system.
Follow these steps to create an Application Project Files:
- In <Working directory>/software/hal_app folder, create a C source code. Name it as helloworld.c.
- In helloworld.c, copy and paste the Hello World application code below.
#include <stdio.h> #include <unistd.h> void looper() { for (int i = 0; i < 1000; ++i) { printf("Hello world, this is the Nios V/m cpu checking in %d...\n",i); } } int main() { looper(); usleep(1000000); printf("Bye world!\n"); fflush(stdout); return 0; }
- Launch the Nios® V Command Shell.
$ niosv-shell
- Execute the command below to generate a BSP folder.
$ niosv-app --bsp-dir=software/hal_bsp --app-dir=software/hal_app \ --srcs=software/hal_app/helloworld.c --elf-name=helloworld.elf
Figure 125. Generated APP Files