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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow
8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
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2.1.4. Second-Stage Bootloader
The second-stage bootloader (SSBL) is the second boot stage for the HPS. The FSBL initiates the copy of the SSBL to the HPS SDRAM. The SSBL typically enables more advanced peripherals such as Ethernet and supports command line interface.
You can create the SSBL from one of the following sources:
- U-Boot
- Intel provides the source code for U-Boot on GitHub.
- UEFI
- Intel provides the source code for UEFI on GitHub.
- RTOS
- Bare Metal application