Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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3.1.2. Secure Device Manager

After the Intel Stratix 10 SoC FPGA exits POR, the SDM samples the MSEL[2:0] pins to determine the boot source. Next, the device configures the SDM I/Os according to the selected boot source interface and the SDM retrieves the configuration bitstream through the interface.
Table 6.  Available SDM Boot Sources for the Intel Stratix 10 SoC FPGA
SDM Boot Source Details
Avalon-ST (x8/x16/x32) Supported
JTAG Supported
Active Serial (AS)/ Quad SPI Supported. SDM only boots in x4 mode for active serial flash and Micron* MT25Q flash. Other supported quad SPI flash devices boot in x1 mode. Once the device initialization code loads into the SDM, the SDM can switch these flash into x4 mode.
The typical configuration bitstream for HPS boot first mode contains:
  • SDM configuration firmware
  • HPS external memory interface (EMIF) I/O configuration data
  • HPS FSBL code and HPS FSBL hardware handoff binary

The SDM completes the configuration of the HPS EMIF I/O and then copies the HPS FSBL to the HPS on-chip RAM.

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