Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition

You can debug the bootloader by using Arm* DS* Intel® SoC FPGA Edition. In order to do that, you need a JTAG connection, so you must enable the HPS Debug Access Port to be accessible through either the SDM or HPS pins.

For more information, refer to the Device and Pin Options section.

For instructions about debugging the Bootloader with Arm* DS* Intel® SoC FPGA Edition, refer to the following web pages on