Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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Document Table of Contents

4.1. Overview

The configuration files are created by the Intel® Quartus® Prime Programming File Generator, using the following inputs:
  • SOF file resulted from compilation of the hardware project in Intel® Quartus® Prime Software
  • HPS First Stage Bootloader (FSBL) hex file resulted from compiling an HPS bootloader
  • Intel® Quartus® Prime Firmware, which ends up running on the SDM
Figure 11. Overview of Configuration File Generation

The resulted configuration files contain the following components which are required for configuring the device:

Table 8.  Components for Configuring the Device
Source Component Description
SOF File HPS IO Configuration Data Used for configuring HPS IOs including HPS DDR
FPGA IO Configuration Data Used for configuring FPGA IOs
FPGA Fabric Configuration Data Used for configuring the FPGA fabric
Handoff Data for SDM Firmware Used to pass parameters to SDM firmware
Handoff Data for HPS FSBL Used to pass parameter to HPS FSBL
Intel® Quartus® Prime SDM Firmware Located at the beginning of configuration bitstream and can be executed as part of the configuration.
Your HPS Software HPS FSBL First software ran on HPS after SDM takes it out of reset

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