Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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Document Table of Contents

6.1. Configuring the FPGA Fabric from U-Boot

The FPGA fabric is configured from U-Boot using data from a RAM buffer with the fpga load <device> <address> <size>.

The GSRD uses HPS boots first mode, with the FPGA fabric being configured by U-Boot running the following script before booting Linux:
setexpr.b reg *0xFFD120DC;
if itest $reg -eq 3;
then bridge enable;
else load mmc 0:1 $loadaddr ghrd.core.rbf; dcache flush; fpga load 0 $loadaddr $filesize; bridge enable;
fi

The script does the following:

  1. Checks if the FPGA fabric is already configured. This can be done with the Intel® Quartus® Prime Programmer, or before hand, on a previous boot before cold resetting the HPS.
  2. If the FPGA fabric is already configured, it enables the bridges by running the brigde enable command, then exits.
  3. If the FPGA fabric is not configured:
    1. It loads the phase 2 core fabric configuration file from the SD card to DDR.
    2. It flushes the data caches so that the data can be accessed by the SDM.
    3. It calls the fpga load <device> <address> <size> command to configure FPGA fabric.
    4. It calls bridge enable to configure the bridges.

    The GSRD is documented on the Intel® Stratix® 10 Soc GSRD web page on the RocketBoards website.

    Note: In boot flow that uses ATF, the first 1 MB of SDRAM is configured as secure region, you must use the address range between 0x100000 (1 MB offset) to 0x20000000 (512 MB offset) for the FPGA configuration file (.rbf).

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