Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022
Public

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2.1.3. First-Stage Bootloader

The first-stage bootloader (FSBL) is the first boot stage for the HPS. In FPGA Configuration First mode, the SDM extracts and loads the FSBL into the on-chip RAM of the HPS. The SDM releases the HPS from reset after the FPGA has entered user mode. After the HPS exits reset, it uses the FSBL hardware handoff file to setup the clocks, HPS dedicated I/Os, and peripherals. Typically, the FSBL then loads the SSBL into HPS SDRAM and passes the control to the SSBL.

You can create the FSBL from one of the following sources:
  • U-Boot secondary program loader (SPL)
    • Intel provides the source code for U-Boot on GitHub.
  • Arm* Trusted Firmware
    • Intel provides the source code for the Arm* Trusted Firmware on GitHub.

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